1. Field of the Invention
The present invention relates to a flash memory having data refresh function and data refresh method of a flash memory where data varying after verify immediately after write or erase can be retrieved and corrected.
2. Description of the Prior Art
FIG. 7 is a block diagram of a flash memory in the prior art disclosed in IEEE Journal of Solid-State Circuits, Vol. 23, No. 5 (October, 1988), pp. 1157-1163.
As shown in FIG. 7, on periphery of a memory array 1 are installed a Y gate 2, a source line switch 3, an X decoder 4 and a Y decoder 5. An address register 6 is connected to the X decoder 4 and the Y decoder 5, and address signals inputted from the outside are inputted to the address register 6. An input data register (writing circuit) 7 and a sense amplifier 8 are connected to the memory array 1 through the Y gate 2. The input data register 7 and the sense amplifier 8 are connected to an I/O buffer 9. In the shown example, eight input/output lines I/O0-I/O7 are connected to the I/O buffer 9. A program voltage generating circuit 10 and a verify voltage generating circuit 11 are installed in the flash memory, and each of the generating circuits 10, 11 generates voltage in level of Vcc, Vpp supplied from the outside and supplies it to the Y gate 2, the decoder 4 or the like. Also a command register 12 and a command decoder 13 setting operation mode by data inputted from the outside are installed in the flash memory. Further, an input signal buffer 14 is installed, and control signals WE (low active), CE (low active), OE (low active) from the outside are inputted to the input signal buffer 14. In addition, in FIG. 7, bar is attached to each control signal, and clearly indicates that it is a low active signal.
FIG. 8 is a sectional view of a memory cell (memory transistor) constituting the memory array of FIG. 7. The memory cell comprises a floating gate 16 formed above a semiconductor substrate 15, a control gate 17, and a source diffusion region (hereinafter referred to as "source") 18 and a drain diffusion region (hereinafter referred to as "drain") 19 formed selectively on the surface of the semiconductor substrate 15. An oxide film 20 between the floating gate 16 and the semiconductor substrate 15 is so thin (about 100 angstrom) that electrons can be moved to the floating gate 16 utilizing the tunnel phenomenon. Next, operation of the memory cell will be described. At program state (writing state of information "0"), program voltage of about 6.5 V is applied to the drain 19, and voltage Vpp (12 V) is applied to the control gate 17, and the source 18 is grounded. Therefore the memory cell is turned on and a current flows. Then avalanche breakdown is produced in the vicinity of the drain 19 and electron/positive hole pair is generated. The positive holes flow through the semiconductor substrate 15 to the ground potential, and the electrons flow in the channel direction into the source 18. However, a part of electrons is accelerated by the electric field between the floating gate 16 and the drain 19 and injected into the floating gate 16. As a result, the threshold voltage of the memory cell rises. This state is defined as storage of the information "0."
On the other hand, erasing is carried out in the state that the drain 19 is opened and the control gate 17 is grounded and voltage Vpp is applied to the source 18. Then the tunnel phenomenon is produced due to the electric field between the source 18 and the floating gate 16, and drawing of electrons in the floating gate 16 occurs. As a result, the threshold voltage of the memory cell falls. This is defined as storage of the information "1."
FIG. 9 is a circuit diagram of the memory array and its peripheral circuit in FIG. 7. As shown in FIG. 9, the memory array comprises 32 blocks from BK1 to BK32 in the shown example, and each block comprises eight data blocks from DB1 to DB8. In each data block, memory cells MC are arranged in matrix form, and in column unit, drains are connected to bit lines BL (BL1-BL3) respectively, and in row unit, control gates are connected to word lines WL (WL1-WL3) respectively. The word lines WL are connected to an X decoder 4, and the bit lines BL are connected to an I/O line 27 through transistors constituting Y gates 2 to whose gates are inputted outputs Y1 -Y3 of a Y decoder 5 respectively. A sense amplifier 8 and an input data register 7 are connected to the I/O line 27, and sources of all memory cells MC are connected through a source line 28 to a source line switch 3.
Next, operation will be described. At first, description will be done in an example that writing (program) is carried out in memory cells MC enclosed by dotted line in FIG. 9. The input data register 7 is activated in response to data inputted from the outside, and program voltage is supplied to the I/O line 27. At the same time, based on address signals (not shown) fetched by the X decoder 4 and the Y decoder 5, the Y decoder 5 makes its output Y1 active state and the Y gate 2, to which the output Y1 is applied, is tuned on, and the X decoder 4 selects the word line WL1 and applies voltage Vpp to it. The source line 28 is grounded by the source line switch 3.
Then current flows through only one memory cell enclosed by the dotted line in FIG. 9, and hot electrons are generated and the threshold voltage becomes high and the information "0" is written.
Erasing is carried out as follows. At first, the X decoder 4 and the Y decoder 5 are non-activated, and all memory cells are made non-selective. That is, the control gate 17 of each memory cell is grounded and the drain 19 is made open, and on the other hand, high voltage is supplied to the source line 28 by the source line switch 3. Thus the threshold voltage of the memory cell is shifted lower by the tunnel phenomenon, and the information "1" is written. Since the source line 28 is common in the chip or in the block, erasing is carried out to all memory cells MC together in the chip or in the block.
Next, reading operation will be described in the case taken as an example that reading is carried out from the memory cells MC enclosed by the dotted line in FIG. 9. At first, address signals are decoded by the Y decoder 5 and the X decoder 4, and the selected Y gate 2 (output Y1 applied) and the word line WL1 become "H" (Vcc). Then the source line 28 is grounded by the source line switch 3. When "0" is written in the memory cell MC, since the threshold voltage is high, even if "H" is supplied to the control gate 17 of the memory cell MC by the word line WL1, the voltage is lower than the threshold voltage of the memory cell, so that the memory cell MC is not turned on and no current flows from the bit line BL1 to the source line 28.
On the other hand, when the memory cell is erased (in the case of "1"), since the voltage "H" applied to the control gate 17 is higher than the threshold voltage of the memory cell, the memory cell is turned on and current flows from the bit line BL1 to the source line 28.
Consequently, the sense amplifier 8 detects whether current flows through the memory cell MC or not, thereby the read data "1" or "0" are obtained.
When one word is constituted by plural bits, in the actual reading operation, one read address is assigned, thereby data of plural bits are read out simultaneously. For example, when one word is constituted by eight bits as in the shown example, in the actual reading operation, one word line and eight bit lines are simultaneously selected in response to assignment of one read address. The selected eight bit lines are corresponding bit lines in the eight data blocks DB1, DB2, . . . DB8 respectively.
Since erasing is carried out by ultraviolet irradiation in the EPROM, when the floating gate becomes neutral electrically, electrons are not drawn further from the floating gate and the threshold voltage of the memory transistor does not become about 1 V or less.
On the other hand, in drawing of electrons utilizing the tunnel phenomenon of the EEPROM or the like used in the flash memory, electrons are drawn excessively from the floating gate thereby it may occur that the floating gate is charged to plus. This phenomenon is called over erase (or excess erase). When the over erase is carried out, since the threshold voltage of the memory transistor becomes minus, the later reading/writing is obstructed.
That is, in the flash memory, even if level of the word line is "L" at non-selective state during reading and level applied to the control gate of the memory transistor is "L," since current flows from the bit line BL to the source line 28 through the memory transistor in over erase, although the memory cell intended to carry out reading on the same bit line has high threshold voltage at "0" write state, current flows through the memory transistor in the over erase, thereby "1" is read out wrongly. Also during writing, since leak current flows through the memory cell in the over erase, the memory cell intended to carry out writing is deteriorated in writing characteristics and further becomes capable of not writing. Therefore in the flash memory, the erasing operation is carried out step by step, and reading is carried out after erasing and it is checked whether the erasing has been carried out correctly (hereinafter referred to as "verify"). If there is any bit being not erased, erasing is carried out again and the erase pulse causing the over erase is prevented from being applied to the memory cell, in conventional method.
FIG. 10 and FIG. 11 are flow charts showing the program and the erase operation including the above-mentioned verify operation, and FIG. 12A-FIG. 12G and FIG. 13A-FIG. 13G are waveform charts showing timing of respective operations. Using these FIG. 10 to FIG. 13 and FIG. 7, each process of erase and program will be described. In conventional flash memory, mode setting of erase and program is carried out by combination of input data. In other words, the mode setting is carried out by input data at rise state of WE (low active).
First, the case of program will be described by FIG. 10 and FIG. 12. At first, voltage Vcc, Vpp is raised (step ST1), and then the control signal WE is dropped.
At rise of next control signal WE, the input data (4OH) indicating the program mode are latched to the command register 12 (step ST2). And then the input data are decoded by the command decoder 13, and the operation mode becomes the program mode. Subsequently, the control signal WE is dropped again and address from the outside is latched to the address register 6, and data DIN are latched to the write circuit 7 at rise of the control signal WE (step ST3). Next, program pulse is generated by the program voltage generating circuit 10 and applied to the X decoder 4 and the Y decoder 5. Thus the program ("0" write) operation is carried out as above described (step ST4).
Next, the control signal WE is dropped, and at rise of the subsequent control signal WE, the input data (COH) indicating the program verify mode are latched to the command register 12 and the operation mode becomes program verify mode (step ST5). Then the program verify voltage (about 7.0 V) is generated within the chip by the erase/program verify voltage generating circuit 11 and applied to the X decoder 4. Since this program verify voltage supplied to the control gate 17 of the memory cell is higher than the voltage 5 V at usual reading state, due to insufficient writing, the memory cell with the threshold voltage lowered can be easily turned on, thereby defective writing can be generated more securely. Next, reading is carried out (step ST6), and if "1" is read out, it can be securely detected as defective writing. If it is defective writing, writing is repeated further. If "0" is read out thereby, decision is effected that the writing is normal (step ST8), the operation mode is set to the read mode and the program is finished.
Next, the case of erase will be described referring to FIG. 11 and FIG. 13. At first, voltage Vcc, Vpp is raised (step ST10), and subsequently "0" is written in all bits using the above-mentioned program flow (step ST11). This is because if an erased memory cell is further erased, the memory cell will become over erase. Next, the control signal WE is dropped and at rise of succeeding control signal WE, erase command (2OH) is inputted (ST12). Subsequently the control signal WE is dropped again, and at rise of succeeding WE, erase confirmation command (2OH) is inputted (step ST13). Then erase pulse is generated within the chip, and until fall of succeeding control signal WE, voltage Vpp is applied to the source 18 of the memory cell through the source line switch 3 (step ST14). At this fall, the address is also latched. Thus erase operation of the memory cell (write of "1") is executed. At rise of succeeding control signal WE, erase verify command (COH) is latched and the operation mode becomes erase verify mode (step ST15). Then erase verify voltage (about 3.2 V) is generated by the erase/program verify voltage generating circuit 11 and applied to the X decoder 4. Since the erase verify voltage supplied to the control gate 17 of the memory cell is lower than the voltage (5 V) at usual reading state, due to insufficient erase, the memory cell with the threshold voltage higher than that of the memory cell in sufficient erase cannot be easily turned on. Consequently, reading after the erase operation is carried out (step ST16), and "0" is read out, thereby, decision is effected that erase is insufficient (step ST17). If erase is insufficient, erase is further repeated. If "1" is read out thereby it is confirmed that erase has been carried out, address is incremented (step ST19), and erase data of next address are verified. If the verified address is the last address (step ST18), the operation mode is set to read mode (step ST20), and the erase operation is finished.
Since the conventional flash memory is constituted as above described, at program state for some memory cell, program verify operation for the memory cell only is carried out immediately after the writing, and verify operation for a memory cell in non-selective state is not carried out.
When a program is carried out for some memory cell, since high voltage Vpp is applied also to a control gate of a memory cell MC in non-selective state connected to the selected word line WL, when the memory cell in non-selective state stores "0," there is a problem in that charge of the floating gate is drawn by the control gate due to the tunnel phenomenon and the stored data may be changed to "1." Or, since Vcc is applied also to drain of a memory cell in non-selective state connected to the bit line BL selected at program state, when the memory cell in non-selective state stores "0," there is a problem in that charge of the floating gate is drawn by the drain due to the tunnel phenomenon and the stored data may be changed to "1."
Further, there is a problem in that charged data within the memory cell become volatile on account of the heat or the like.
Such phenomenon is frequently generated that data cannot be held as a result that the memory size is more decreased attendant on large capacity of a memory.
Further, when the flash memory is used as a file memory, the number of times of rewrite of the memory is increased, and in each rewrite, disturb stress for cells in non-selective state connected to the selected word line WL or the selected bit line BL is added as above described, and holding of data becomes difficult.
In the prior art, a flash memory which holds data varied to defective data after the verify operation of the data immediately after the write of data or immediately after the erase of data is found only by test before the shipment. If a defective flash memory is found then, since the flash memory must be inevitably abandoned, there is a problem in that manufacturing of the flash memory comes to nothing resulting in rise of the memory price.